1. Field of the Invention
The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer capable of reducing a lock tine by lowering a frequency of a frequency oscillator with the use of a divider and configuring a phase locked loop (PLL) with a digital block.
2. Description of the Related Art
In the fields of mobile communications, frequency synthesizers are widely used to generate stable frequencies for data transmission and reception. Frequency oscillators may include a phase locked loop (PLL) and a voltage controlled oscillator (VCO). The PLL may lock an output frequency of the VCO in a negative feedback control scheme.
Digital frequency oscillators for wideband tuning according to the related art have used an adaptive frequency correction loop. The frequency correction loop may include a VCO, a main divider, a frequency detector, and a state machine. An output frequency of the VCO is controlled by an input bit value. The output frequency of the VCO linearly increases with an increase of a digital control bit value B[k]. The main divider generates a division signal by dividing an oscillation frequency waveform outputted from the VCO. The frequency detector is configured with a counter, and calculates a difference in clock numbers between the division frequency and a reference frequency during n clocks of the reference frequency. The state machine receives the difference of number of clocks from the frequency detector during n clocks of the reference frequency, determines a frequency state between the reference frequency and the division frequency, and readjusts the output bit value. By repeating those procedures, the output frequency of the VCO is shifted to a frequency corresponding to a multiplication of the division value of the main divider and the reference frequency.
However, since the frequency correction loop readjusts the VCO input bits by simply detecting the state of the frequency difference through the state machine, it takes a long time to shift to a desired frequency band when the input bit for the frequency correction of the VCO is large.